# This is an SPD board with a single STM32F030F4Px chip
#
# Generated by System Workbench for STM32
# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s)

source [find interface/stlink.cfg]

set WORKAREASIZE 0x1000

transport select "hla_swd"

set CHIPNAME STM32F030F4Px
set BOARDNAME SPD

# CHIPNAMES state
set CHIPNAME_CPU0_ACTIVATED 1

# Enable debug when in low power modes
set ENABLE_LOW_POWER 1

# Stop Watchdog counters when halt
set STOP_WATCHDOG 1

# STlink Debug clock frequency
set CLOCK_FREQ 4000

# use software system reset
reset_config none
set CONNECT_UNDER_RESET 0

# BCTM CPU variables



source [find target/stm32f0x.cfg]
